Freescale公司的 i.MX23是低功耗高性能的多媒体应用处理器,集成了ARM926EJ-S CPU,工作频率454MHz,提供电池长寿命,最少的外接元件,具有极好的软件开发和调试支持,特别适合需要音频/视频译码和丰富显示的多媒体应用.而 i.MX23 EVK评估板是单独可用的板,支持应用软件开发,目标板调试和选择电路卡.4.3吋LCD触摸屏和评估板一起使用.本文介绍了i.MX23 硬件特性,系统框图和方框图,i.MX23 EVK 评估板主要特性,功能框图和电路图,材料清单.
The i.MX23 is an applications processor targeted at devices that require low power, high performance, high integration and quality audio and video playback.
The i.MX23 offers long battery life, minimal external components through integration, high processing performance, and excellent software development and debug support. The i.MX23 is especially suited for multi-media applications requiring audio/video decode and rich display support. These requirements are achieved via the high-performance CPU, pixel processing and integrated display and TV-Out hardware.
The i.MX23 features low power consumption to enable long battery life in portable applications. The integrated power management unit includes a high-efficiency, on-chip DC-DC converter. The power management unit also includes an intelligent battery charger for Li-Ion cells and is designed to support adaptive voltage control (AVC), which can reduce system power consumption by half. AVC also allows the chip to operate at a higher peak CPU operating frequency than typical voltage control systems. The DC-DC converters and the clock generator can be reprogrammed on-the-fly to trade off power versus performance dynamically.
To provide the maximum application flexibility, the i.MX23 integrates a wide range of I/O ports. It can efficiently interface to nearly any type of flash memory, serial peripheral bus, or LCD. It is also ready for advanced connectivity applications such as Bluetooth and WiFi via its integrated 4-bit SDIO controller and high-speed (3.25 Mb/s) UARTs.
The i.MX23 also integrates an entire suite of analog components, including a high-resolution audio codec with headphone amplifier, 16-channel 12-bit ADC, 10-bit Video DAC, Mono Speaker Amplifier, high-current battery charger, linear regulators for 5-V operation, high-speed USB Host PHY, and various system monitoring and infrastructure systems.
An ARM 926 EJ-S CPU with 32 Kbytes of on-chip SRAM and an integrated memory management unit provides the processing power needed to support advanced features such as audio cross-fading, as well as still picture and video decoding.
Execution always begins in on-chip ROM after reset, unless overridden by the debugger. A number of devices are programmed only at initialization or application state change, such as DC-DC converter voltages, clock generator settings, etc. Certain other devices either operate in the crystal clock domain or have significant portions that operate in the crystal clock domain, e.g., ADC, DAC, PLL, etc. These devices operate on a slower speed asynchronous peripheral bus. Write posting in the ARM core, additional write post buffering in the peripheral AHB, and set/clear operations at the device registers make these operations efficient.
ARM926 CPU Running at 454 MHz
— Integrated ARM926EJ-S CPU
— 16-Kbyte data cache and 16-Kbyte instruction cache
— ARM Embedded Trace Macrocell (ETM CoreSight 9) (169BGA only)
— One-wire JTAG interface
— Resistor-less boot mode selection using integrated OTP values
32 Kbytes of Integrated Low-Power On-Chip RAM
64 Kbytes of Integrated Mask-Programmable On-Chip ROM
1 Kbit of On-Chip One-Time-Programmable (OCOTP) ROM
Universal Serial Bus (USB) High-Speed (Up to 480 Mb/s), Full-Speed (Up to 12 Mb/s)
— Full-speed/high-speed USB device and host functions
— Fully integrated full-speed/high-speed Physical Layer Protocol (PHY)
— Mass storage host-capable (uncertified by USB-IF)
Power Management Unit
— Single inductor DC-DC switched converter with multi-channel output supporting Li-Ion batteries.
— Features multi-channel outputs for VDDIO (3.3 V), VDDD (1.2 V), VDDA (1.8 V), VDDM (2.5V) and regulated 4.2V source.
— Direct power from 5-V source (USB, wall power, or other source), with programmable current limits for load and battery charge circuits.
— Silicon speed and temperature sensors enable adaptive power management over temperature and silicon process.
— Stereo headphone DAC with 99 dB SNR
— Stereo ADC with 85 dB SNR
— Stereo headphone amplifier with short-circuit protection and direct drive to eliminate bulky capacitors
— Mono speaker amplifier (169-Pin BGA only) providing up to 2W rms output, running directly from the battery.
— Amplifiers are designed for click/pop free operation.
— Two stereo line inputs
— Microphone input
— SPDIF digital out
16-Channel Low-Resolution ADC
— 6 independent channels and 10 dedicated channels
— Resistive touchscreen controller
— Temperature sensor controller
— Absolute accuracy of 1.3%
— Up to 0.5% with bandgap calibration
— Read-only unique ID for digital rights management algorithms
— Secure boot using 128-bit AES hardware decryption
— SHA-1 hashing hardware
— Customer-programmed (OTP) 128 bit AES key is never visible to software.
External Memory Interface (EMI)
— Provides memory-mapped (load/store) access to external memories
— Supports the following types DRAM:
– 1.8-V Mobile DDR
– Standard 2.5V DDR1
Wide Assortment of External Media Interfaces
— Up to four NAND flash memories with hardware management of device interleaving
— High-speed MMC, secure digital (SD)
— Hardware Reed-Solomon Error Correction Code (ECC) engine offers industry-leading protection and performance for NANDs.
— Hardware BCH ECC engine allowing for up to 20-bit correction and programmable redundant area.
Dual Peripheral Bus Bridges with 18 DMA Channels
— Multiple peripheral clock domains save power while optimizing performance.
— Direct Memory Access (DMA) with sophisticated linked DMA command architecture saves power and off-loads the CPU.
Highly Flexible Display Controller
— Up to 24-bit RGB (DOTCK) modes
— Up to 24-bit system-mode including VSYNC and WSYNC modes.
— Up to VGA (640x480) resolution at 60Hz LCD panel support
— 8-bit data ITU-R BT.656 D1 digital video stream output mode (PAL/NTSC), with on-the-fly RGB to YCbCr color-space-conversion.
— Flexible input formats
Pixel Processing Pipeline (PXP)
— Provides full path from color-space conversion, scaling, alpha-blending to rotation without intermediate memory access
— Bi-linear scaling algorithm with cropping and letterboxing
— Alpha-blend, BITBLT, color-keying
— Memory efficient block-based rotation engine
— Supports up to eight overlays
Integrated TV-Out Support
— Integrated PAL/NTSC TV-encoder fully pipelined to display controller’s D1 resolution output stream
— Integrated low-power 10-bit Video DAC (VDAC) for composite analog video output.
Data Co-Processor (DCP)
— AES 128-bit encryption/decryption
— SHA-1 hashing
— High-speed memory copy
Three Universal Asynchronous Receiver-Transmitters (UARTs)
— Two high-speed application UARTs operating up to 3.25 Mb/s with hardware flow control and dual DMA.
— Debug UART operates at up to 115Kb/s using programmed I/O.
— DMA control of an entire EEPROM or other device read/write transaction without CPU intervention
Dual Synchronous Serial Ports (for SPI, MMC, SDIO, Triflash)
— Up to 52MHz external SSP clock for all modes, including SPI
— 1-bit, 4-bit and 8-bit MMC/SD/SDIO modes
— Compliant with SDIO Rev. 2.0
— SPI with single, dual and quad modes.
Four-Channel 16-Bit Timer with Rotary Decoder
Five-Channel Pulse Width Modulator (PWM)
— Alarm clock can turn the system on.
— Uses the existing 24-MHz XTAL for low cost or optional low power crystal (32.768 kHz or 32.0 kHz), customer-selectable via OTP.
Dual Serial Audio Interface (SAIF), Three Stereo Pairs
— Full-duplex stereo transmit and stereo receive operations
— Cell phone baseband processor connection and external ADCs and DACs
— Bluetooth hands-free connection
— Analog I/O for peripheral bus breakouts
— I2S, left-justified, right-justified, and non-standard formats
Customer-Programmable One-Time-Programmable (OTP) ROM via Integrated eFuse Block
— Resistor-less boot mode selection
— 128-bit boot mode crypto key
— Boot mode specification of NAND characteristics for device that the customer is soldering to the board. This means no more costly delays waiting for new device support in the boot ROM.
— Fully software-programmable and accessible
Flexible I/O Pins
— All digital pins have drive-strength controls
— Most non-EMI digital pins have general-purpose input/output (GPIO) mode.
Offered in 128-Pin Low-Profile Quad Flat Pack (LQFP), and 169-Pin Ball Grid Array (BGA)